1. Field of the Present Invention
The present invention relates to the field of integrated circuit design and more particularly to the field of integrated circuit design verification systems.
2. History of Related Art
In the field of integrated circuit design, formal verification refers to the process of rigorously proving that a design satisfies its specification. Typically, the specification of a verification problem includes a netlist-based representation of the design and a set of expected values for specified nets under specified conditions. As an example, a verification problem may include determining whether a state exists in which a CHECKSTOP net is asserted, where an asserted CHECKSTOP indicates a fault. Using formal verification, one either finds a counterexample trace depicting a sequence of values of the nets over time, similar to a simulation trace, that leads to an assertion of the CHECKSTOP net or proves that no such trace exists.
Formal verification is often performed using state space search algorithms. Such algorithms include unbounded and bounded exhaustive searches. Bounded exhaustive searches try to find an assertion of CHECKSTOP that can occur within N time steps from an initial state of the design. Unbounded exhaustive algorithms increase N until no states are encountered that have not already been encountered for smaller values of N (a condition termed “fixed-point”). If no path from an initial state to a violating state (a state in which CHECKSTOP is asserted) is encountered before fixed-point is reached, then correctness can be inferred.
The number of verification cycles required to perform an exhaustive state space search increases exponentially with the number of state holding elements or registers. This exponential relationship makes formal verification impractical for designs containing a very large number of state holding elements. As a result, design verification engineers have developed innovative techniques for simplifying the formal verification tasks. Two such techniques are incremental verification and constraint-based verification.
Incremental verification is a verification technique that is applicable when an existing design (the old design) is modified to create a new design. Incremental verification is motivated by the desire to re-use the results of verification performed on the old design. It is quite common in the design of integrated circuits that the netlist of an old design shares substantial similarity with netlists for the new design because design changes frequently affect a relatively small percentage of the nets in a design, especially later in the design cycle. When this is the case, it is usually easier to verify that the new design and the old design share a common behavior than to verify the new design “from scratch.” Incremental verification takes advantage of this reality by creating a composite netlist that includes the netlists of the old and new design, creating a set of targets that indicate differences in behavior between the old and new designs, and verifying that none of these composite targets can be asserted. Additional detail of an incremental verification may be found in co-pending and commonly assigned U.S. Patent Application of Baumgartner et al. entitled Incremental, Assertion-Based Design Verification, U.S. patent application Ser. No. 10/782,673, filed Feb. 19, 2004, Publication No. 20050188337, published Aug. 25, 2005, which is incorporated by reference herein (referred to as the Incremental Verification Application).
Constraint-based verification is a verification technique in which constraints are applied to one or more nets of the design to limit verification coverage to a subset of the total state space of a design. The constraints applied to the design typically reflect conditions that cannot or are not permitted to occur during operation of the design in the field. For example, verification of a design may be constrained to only those cases where data inputs to the design exhibit either odd or even parity. Constraints are enforced during verification by creating and monitoring constraint nets that are indicative of the specified constraints. In one implementation, verification is performed only for states/cycles where all of the constraint nets are true (evaluate to “1”). Constraint-based verification reflects the reality that many theoretically achievable states in a design need not be formally verified because, in operation, those states are prohibited from occurring. An implementation of constraint-based verification is described in co-pending and commonly assigned U.S. patent application of Baumgartner et al., entitled Using Constraints In Design Verification, U.S. patent application Ser. No. 11/236,451, filed Sep. 27, 2005.
Unfortunately, the use of incremental verification paradigms in the presence of constraints is a difficult problem because constraints in one of the designs (e.g., the new design) may restrict the evaluation of the other design. Because improperly restricting one of the designs may result in incorrect results such as concluding that verification results for the old design are applicable to the new design, incremental verification techniques are not directly transferable in the presence of design constraints. It would be desirable to implement methods, systems, and software for combining the benefits of incremental and constraint based verification. More specifically, it would be desirable to implement incremental design verification principles to designs that have been verified using constraints.